| 摘要 |
PROBLEM TO BE SOLVED: To provide the hysteresis circuit with a simple configuration in which current consumption by a through-current is reduced. SOLUTION: The CMOS hysteresis circuit 10 is configured such that PMOS transistors(TRs) 11, 12 and NMOS TRs 13, 14 are connected in series between a power supply voltage and a reference potential, respective gates are connected in common to an input terminal IN, a connecting point of the PMOS TR 12 and the NMOS TR 13 is connected to an output terminal OUT via an inverter circuit 15, a PMOS TR 16 and an NMOS TR 17 are connected respectively in parallel with the PMOS TR 11 and the NMOS TR 14 and gates of the PMOS TR 16 and the NMOS TR, 17 are connected to the output terminal. |
