发明名称 |
Synchronous semiconductor memory device which allows switching of bit configuration |
摘要 |
A synchronous DRAM includes a selector which supplies 2 bits of serial data signals from one data input/output terminal to two input/output line pairs as parallel data signals in x8 configuration mode, and supplies 2 bits of parallel data signals from both data input/output terminals directly to two input/output line pairs in x16 configuration mode. Therefore, the synchronous DRAM allows switching of bit configuration, and it takes 2-bits prefetch configuration in x8 configuration mode, and signal pipeline configuration in x16 configuration mode.
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申请公布号 |
US5764590(A) |
申请公布日期 |
1998.06.09 |
申请号 |
US19960735149 |
申请日期 |
1996.10.22 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
IWAMOTO, HISASHI;KONISHI, YASUHIRO |
分类号 |
G11C11/407;G11C7/10;G11C11/401;G11C11/408;(IPC1-7):G11C8/00 |
主分类号 |
G11C11/407 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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