发明名称 Self-aligned twin well process
摘要 A method is provided for forming planar, self-aligned spaced-apart wells without a high temperature oxidation step to form an ion barrier. The method comprises preparing a substrate with a silicon dioxide-polysilicon-silicon dioxide barrier layer that can be etched to expose different sublayers of the barrier at selected junctures in the production process. A single masking step defines the location of a first set of wells on the prepared substrate. The outer silicon dioxide layer is etched to expose the polysilicon layer at the selected locations, and the substrate is implanted to form the first set of wells. Following ion implantation, the substrate photo-resist is removed, and the substrate is exposed to a germanium-silicon mixture under conditions selected to preferentially deposit a germanium-silicon alloy barrier layer on the exposed polysilicon layer. The germanium-silicon alloy masks the first set of doped wells against subsequent etching and an ion implantation step that forms the second set of doped wells. Since the locations at which the germanium-silicon alloy deposits are defined by the locations of the first set of wells, the second set of wells is automatically aligned with respect to the first set of wells, and about 500 ANGSTROM , thick.
申请公布号 US5763302(A) 申请公布日期 1998.06.09
申请号 US19960704472 申请日期 1996.08.20
申请人 LSI LOGIC CORPORATION 发明人 KAPOOR, ASHOK K.
分类号 H01L21/205;H01L21/266;H01L21/8238;H01L27/092;(IPC1-7):H01L21/823 主分类号 H01L21/205
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