Delay compensation/resynchronization circuit for phase lock loops

摘要

A circuit that compensates for delays induced by clock generation logic and distributed clock drivers (120...130) in phase lock loop applications is disclosed. The circuit is a phase lock loop (PLL) which contains a clock synchronization circuit (260) that operates to synchronize a transition edge of a signal generated by a frequency divider (135) against a distributed clock signal (145) generated by a clock output driver (130) of the circuit. The synchronization occurs unless the clock synchronization circuit (260) is disabled. <IMAGE>