Circuitry with gate line crossing semiconductor line at two or more channels

摘要

Circuitry formed at a surface of a substrate includes first and second lines (180,182) in first and second layers of the circuitry. The first line (180) includes semiconductor material and extends between first and second connecting points (190,192) at which it connects electrically to other components. The second line (182) is connected (188) to receive a gate signal, and crosses the first line (180) in two or more channel regions (184,186). The first line (180) includes a channel in each channel region, and the channels are in series. The second line (182) conducts the gate signal to all of the channel regions. The first line (180) includes charge carrier sources and destinations positioned so that conductivity of the first line between the first and second connecting points is controlled by the gate signal. The first layer can be polysilicon, and the second layer can be polysilicon or metal. The first line can be undoped in the channel regions (184,186) but heavily doped in other areas. Each of the first and second lines can include an angle of approximately 90 DEG between two of the channel regions, forming a Crossed-L configuration. In an active matrix display or other array with M scan lines and N data lines, the first line (180) can be connected to the nth data line (172) and the second line (182) can receive the gate signal from the mth scan line (170).