| 摘要 |
<p>The erasing and read techniques use connection sequences to produce better performance. For the erasing process, the source connection of the floating grid and drain of the integrated circuit transistor are earthed, and the command grid given high voltage programming (VPP) above the integrated circuit voltage feed. Programming is used to erase the first cell, and remove the electrical charges in stages. In read, the transistor source is earthed, and the amplifier connected to the transistor drain and the command grid given a command voltage between the earth voltage and feed voltage. The second cell is not connected.</p> |
