| 摘要 |
A mechanism and method providing an early read operation of data associated with an instruction dispatched for execution to provide data dependency information in time to be used for scheduling subsequent instructions which may execute back-to-back in a pipeline microprocessor. The present invention provides the above functionality for instructions following single cycle instructions. The present invention provides immediate scheduling of instructions that are dependent on single cycle instructions. A reservation station holds the information pertaining to instructions that are to be scheduled for execution. The early read logic is implemented so that an address of a destination register associated with a dispatched single cycle instruction can be read from the associated entry of the reservation station early enough so as to be used and compared against the addresses of source registers of other instructions waiting to be scheduled (a CAM match). In this way, a subsequent instruction can be made ready for scheduling within a single clock cycle following the dispatch stage of the previously dispatched instruction to achieve maximum throughput efficiency. The present invention utilizes a non-clocked read memory to perform the early read operation of the address of the destination register of the reservation station while the remainder of the reservation station utilizes a clocked-read implementation and memory. |
