发明名称 INTEGRATED CIRCUIT FOR BALLAST WITH SHUT DOWN FUNCTION
摘要 PROBLEM TO BE SOLVED: To prevent the simultaneous continuity of first and second semiconductor devices by arranging a circuit delaying the output of a latch circuit, a driver circuit for driving a gate, and a shut down latch circuit for stopping the output of the driver circuit in a driving integrated circuit of first and second MOS gate type power semiconductor devices. SOLUTION: Dead time delay circuits 126, 130 for delaying 1μsec the output of a latch circuit 120 are formed in an integrated circuit for driving first and second MOS gate type power semiconductor devices. Gate drivers 138, 142 drive so as to make the gates of the first and second devices on and off, and supply an output signal to a load circuit connected to a half bridge. A shut down latch circuit 124 stops the output of the drivers 138, 142 when oscillation stop is troubled, and automatically re-starts it when the trouble state is finished. Re-starting is made possible when the driving circuit is troubled or a lamp is replaced without damaging constituting components.
申请公布号 JPH10149889(A) 申请公布日期 1998.06.02
申请号 JP19970284928 申请日期 1997.10.17
申请人 INTERNATL RECTIFIER CORP 发明人 HOUK TALBOTT M
分类号 H05B41/24;H05B41/285;(IPC1-7):H05B41/24 主分类号 H05B41/24
代理机构 代理人
主权项
地址