| 摘要 |
A control system operates in a pipelined mode for executing multiple clock cycle instructions and in an open loop mode for executing single clock cycle instructions. A plurality of electrical functional units are capable of executing single clock cycle instructions and multiple clock cycle instructions that are individually addressed and applied thereto by a processor. The functional units generate current operational statuses after each clock cycle. A status indicator applies new operational statuses of the functional units to the processor. A status memory stores previous operational statuses of the functional units. A control unit controls the status indicator to apply the previous operational statuses to the processor as the new operational statuses after one of the single clock cycle instructions has been applied to the functional units. The control unit further controls the status indicator to apply the current operational statuses to the processor as the new operational statuses after one of the multiple clock cycle instructions has been applied to the functional units. In this manner, the single cycle instructions do not go through the pipeline, and their propagation times are not limited by the pipeline latency.
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