发明名称 |
Synchronous memory with pipelined write operation |
摘要 |
There is provided a method of controlling an internal address signal of an RAM in which a late-write method is realized on a chip. Two sets of address registers for reading and writing are provided for each address and further a middle register is provided between the two sets of address registers. The middle register is controlled by a signal formed by obtaining the AND result of a clock signal and a write enable signal and the two sets of address registers for reading and writing are controlled only by the clock signal. A selection circuit selects outputs of the two sets of address registers as an input in accordance with the write enable signal to control an internal address.
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申请公布号 |
US5761150(A) |
申请公布日期 |
1998.06.02 |
申请号 |
US19960651873 |
申请日期 |
1996.05.21 |
申请人 |
HITACHI, LTD. |
发明人 |
YUKUTAKE, SEIGOH;MITSUMOTO, KINYA;AKIOKA, TAKASHI;IWAMURA, MASAHIRO;AKIYAMA, NOBORU |
分类号 |
G11C11/413;G06F12/00;G11C7/10;G11C8/06;G11C11/401;G11C11/407;G11C11/418;(IPC1-7):G11C8/00;G11C7/00 |
主分类号 |
G11C11/413 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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