发明名称 VARIABLE FREQUENCY DIVIDER
摘要 PROBLEM TO BE SOLVED: To improve the precision of a signal waveform by selecting a count-up signal corresponding to a register optionally as a timing signal for output signal inversion so as to make a multichannel scale unchange and to obtain a minute duty ratio. SOLUTION: A register 50 that receives a count-up signal CU 1 and an output of a zero detector 16 detecting it that a count of a register R1 reaches zero provides an output of a signalα. On the other hand, a register 52 selects any of count-up signals CU2-CU4 as a timing signal that is used to invert an output signal P1 from an H level into an L level through a decode circuit 54 and a selector 56. In the case of setting by the register 52 to use the signal CU3, the decode circuit 54 gives a signalβto an AND circuit 62 to switch a selector 58 so as to select the signal CU 3. Thus, the count-up signal that is selected optionally is used for a timing signal to invert the output signal.
申请公布号 JPH10150359(A) 申请公布日期 1998.06.02
申请号 JP19960308049 申请日期 1996.11.19
申请人 KAWASAKI STEEL CORP 发明人 FUJIMAKI YUTAKA
分类号 H03K21/00;(IPC1-7):H03K21/00 主分类号 H03K21/00
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