发明名称 |
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE |
摘要 |
<p>PROBLEM TO BE SOLVED: To provide a circuit which is improved in data retention characteristics, capable of relieving faults, changing functions or trimming owing to easy manufacturing and high reliability by providing a barrier layer covering the floating gate partially or wholy in a non-volatile memory element of single-layer gate structure. SOLUTION: The memory mat MR-MAT is provided with memory elements for mask ROM in the form of matrix. The memory mat PR-MAT is provided with a matrix of single-layer gate structured non-volatile memory elements for relieving defective data. The word line of the memory mat MR-MAT is selected by an X decoder circuit XDC. The data line of the memory mat MR- MAT is connected to the common data line by a column switch gate MR-YGT. The column switch gate MR-YGT operates to connect one data line for each output mat from the inside of the memory mat MR-MAT to the common data line.</p> |
申请公布号 |
JPH10149696(A) |
申请公布日期 |
1998.06.02 |
申请号 |
JP19970323887 |
申请日期 |
1997.11.10 |
申请人 |
HITACHI LTD;HITACHI VLSI ENG CORP |
发明人 |
KURODA KENICHI;TAKEDA TOSHIFUMI;MORIUCHI HISAHIRO;SHIRAI MASAKI;SAKAGUCHI JIRO;MATSUO AKINORI;YOSHIDA SEIJI |
分类号 |
G11C16/06;G11C29/00;G11C29/04;H01L21/8247;H01L27/10;H01L27/115;H01L29/788;H01L29/792;(IPC1-7):G11C29/00;H01L21/824 |
主分类号 |
G11C16/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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