Bus bridge circuit flushing buffer to a bus during one acquire/relinquish cycle by providing empty address indications

摘要

A bridge circuit adapted to be associated with a first faster bus circuit and a second slower bus circuit which bridge circuit includes a first path for transferring data between the first and second buses including a plurality of individual buffers each capable of storing a plurality of separately addressed increments of data destined for a plurality of sequential addresses, apparatus for storing data in the buffers at addresses provided by a bus master on the second bus, apparatus for detecting when data in a buffer is ready to be transferred to the first bus, apparatus for flushing any buffer which contains data ready to be transferred to the first bus, and apparatus for transferring data from the second bus to another of the plurality of buffers when a first buffer contains data ready to be transferred to the first bus until all of the buffers contain data ready to be transferred to the first bus