Memory implemented error detection and correction code using memory modules
摘要
A method and apparatus for performing digital signal error detection and correction through the use of a string of received incoming system address bits. The incoming address bits are divided into groups according to whether they contain a high value of "1" or a low value of "0". At least one address parity bit is then generated from each group and used in checking the integrity of data received. Errors are corrected and detected through assignment of data bits to different modules in a memory of a computer system having symbols which are b bits in length.
申请公布号
US5761221(A)
申请公布日期
1998.06.02
申请号
US19950570447
申请日期
1995.12.11
申请人
INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人
BAAT, KLAUS RUEDIGER;CHEN, CHIN-LONG;HSIAO, MU-YUE;LIPPONER, WALTER HEINRICH;SHEN, WILLIAM WU