| 摘要 |
In a cache memory of a set associative type, a cache-miss rate measuring circuit 140 measures the cache-miss rate during way access operation, the way number control circuit 150 determines the number of ways to be accessed based on a change of the measured cache-miss rate and transfers the determined information about the ways to be accessed to the power control circuit 160. The cache memory controls as follows: When the cache-miss rate is decreased under the condition that the number of ways is reduced, the number of ways to be accessed is changed to the original number of ways and when the cache-miss rates before and after switching of the number of ways are not changed, the number of ways to be accessed is decreased, and power consumption reduced. |
