发明名称 |
Clock skew minimization system and method for integrated circuits |
摘要 |
A precise and highly controllable clock-distribution network is provided on one active substrate to distribute clock signals with minimal skew to another active substrate by connecting the substrates together face-to-face using flip-chip technology. Since the clock-distribution substrate is sparse, "quiet busses" are provided on the sparse substrate to facilitate the high-speed transfer of data over relatively long distances. Low-power devices (e.g., DRAM) can be provided on one substrate for use by higher-power logic (e.g., a processor) on another substrate with minimal interconnection distance.
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申请公布号 |
US5760478(A) |
申请公布日期 |
1998.06.02 |
申请号 |
US19960700261 |
申请日期 |
1996.08.20 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
BOZSO, FERENC MIKLOS;EMMA, PHILIP GEORGE |
分类号 |
H01L21/60;G06F1/10;H01L23/52;H01L25/065;H01L25/07;H01L25/18;H01L27/02;(IPC1-7):H01L23/48;H01L29/40;H01L23/02 |
主分类号 |
H01L21/60 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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