AN ADDRESS TRANSITION DETECTION CIRCUIT

摘要

An address transition detection (ATD) circuit comprises a first (102) and a second (DDS) circuit and an interval timer (300). First circuit (102) receives on a first input (1-1) a change signal corresponding to a transition on one or more address bus lines, and in response transitions the output (O) from a first state to a second state. First circuit (102) receives a reset signal at a second input (1-2) to return the output (O) to the first state. The interval timer (300) has an output coupled to the second input (1-2) of the first circuit (102) and, upon receiving a signal at its input, generates the reset signal at its output after a timed interval. The second circuit (DDS) couples the change signal to the input of the interval timer (300).