发明名称 Taktsignalübertragung über einen asynchronen Datenkanal
摘要 <p>An input clock signal associated with an input data signal is divided by a predetermined integer N, to form a sub-rate clock signal. The sub-rate clock signal is sampled and transmitted along with the input data over an asynchronous data channel. At the receiver, the resulting sub-rate clock signal is received and coupled to a phase lock loop which generates a recovered clock signal of the same frequency and substantially in phase with the input clock signal. &lt;IMAGE&gt;</p>
申请公布号 DE69316424(T2) 申请公布日期 1998.05.28
申请号 DE1993616424T 申请日期 1993.04.01
申请人 AT & T CORP., NEW YORK, N.Y., US 发明人 HONEA, WILLIAM KEITH, DENVER, COLORADO 80223, US
分类号 H04J3/06;H04L7/00;H04L7/033;H04L12/70;H04L25/30;H04N7/66;H04N21/242;H04N21/43;(IPC1-7):H04J3/06 主分类号 H04J3/06
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