| 摘要 |
<p>The phase-locked loop circuit (40) includes a phase-frequency detector stage (41) having a first and a second gain value (KdH, KdL) enabled selectively; a first and a second loop filter (52, 50) having a first (H(s)H) and, respectively, second (H(s)L) transfer function enabled selectively, and each having a respective output (53, 51) connected to a controlled oscillator (60); a selection input (65) receiving a selection signal (SEL) having a first and a second level for selectively enabling the first gain value (KdH) and the first filter element (52) in a first operating mode, and the second gain value (KdL) and the second filter element (50) in a second operating mode, so that, in the first operating mode, the circuit has a high open-loop response gain and hence a wide band, and, in the second operating mode, the circuit has a narrow band and a higher damping factor for also ensuring stability in the second operating mode. <IMAGE></p> |
