| 摘要 |
<p>A chip carrier is formed by a plurality of functional substrates, such as a signal connection substrate (105, 410, 802), a capacitor substrate (104, 419, 812-2), a resistor substrate (103, 420, 812-1) and a power supply substrate (102, 421). The several substrates are individually manufactured and tested before they are assembled. Advantageously, the manufacturing and testing of the substrates are carried out in parallel, so as to reduce manufacturing time. Each substrate has a top interconnect layer (202) and a bottom interconnect layer (201). Each interconnect layer has a plurality of bond pads in an identical pattern. The pads are formed using the same design rules, structure, pitch, diameter and fabrication process for each layer. This identity allows the different functional substrates to be electrically interchanged without changing the interconnection layers, although changes internal to the substrate may be required. <IMAGE></p> |
