| 摘要 |
An arrangement (6) for encrypting/decrypting data comprising: random access memory (12) for holding the data; a processor (10) for processing the data, the processor having a memory map including a first portion (12.0) mapped onto the random access memory and a second portion (12.1); and control means (18, 34, 26) coupled to receive an instruction to write data to an address in the second portion of the memory map and in response thereto to write the data in a predetermined permuted form to an associated address in the random access memory, whereby data read from said associated address in the random access memory is an encrypted/decrypted version of the data written to said address in the second portion of the memory map. |
