发明名称 Multi-bit A/D converter having reduced circuitry
摘要 The A/D converter comprises a resistor series (30), a plurality of first comparators (1) and a plurality of second comparators (2). Resistor series (30) has a plurality of resistors(R) connected in series between two terminals to which predetermined reference voltages are applied. First comparator (1) compares a node voltage between resistors and an analog voltage signal to be compared. Second comparator (2) compares an average voltage of the two node voltages across each resistor R and the analog voltage signal. First and second comparators (1,2) are disposed alternatively.
申请公布号 US5757303(A) 申请公布日期 1998.05.26
申请号 US19960649063 申请日期 1996.05.16
申请人 MOTOROLA, INC. 发明人 NAKATANI, YUICHI;TAKAHASHI, SATOSHI;AIURA, MASAMI
分类号 H03M1/14;H03M1/20;H03M1/36;(IPC1-7):H03M1/36 主分类号 H03M1/14
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