发明名称 |
System and method for indicating that a processor has prefetched data into a primary cache and not into a secondary cache |
摘要 |
Within a data processing system implementing L1 and L2 caches and stream filters and buffers, prefetching of cache lines is performed in a progressive manner. In one mode, data may not be prefetched. In a second mode, two cache lines are prefetched wherein one line is prefetched into the L1 cache and the next line is prefetched into a stream buffer. In a third mode, more than two cache lines are prefetched at a time. In the third mode cache lines may be prefetched to the L1 cache and not the L2 cache, resulting in no inclusion between the L1 and L2 caches. A directory field entry provides an indication of whether or not a particular cache line in the L1 cache is also included in the L2 cache.
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申请公布号 |
US5758119(A) |
申请公布日期 |
1998.05.26 |
申请号 |
US19950518347 |
申请日期 |
1995.08.23 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORP. |
发明人 |
MAYFIELD, MICHAEL JOHN;NGUYEN, TRINH HUY;REESE, ROBERT JAMES;VADEN, MICHAEL THOMAS |
分类号 |
G06F12/08;(IPC1-7):G06F12/08 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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