| 摘要 |
A data processing apparatus in which the CPU can have different data bus widths is described. A variable power source is provided to supply a proper voltage to an installed CPU, and a CPU module has a feedback resistor that is connected to feedback terminals of the CPU module. By changing the resistance value of the feedback resistor in each CPU module, a proper output voltage can be provided to the installed CPU. The CPU module is provided with a terminal that generates a module determination signal used for making a determination of a module of the installed CPU module. Expanded RAM is provided with a terminal that generates a memory determination signal used for making a determination as to whether or not a memory is expanded. A memory controller and a bus control section perform a bus control function appropriate to the installed CPU and the installed memory in accordance with the module determination signal and the memory determination signal.
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