| 摘要 |
Circuitry combines a first operand A0, a second operand A1, and a third operand X in a blend function to produce a result Z. The result Z has a value equal to X*A0+(1-X)* A1. The circuitry includes a plurality of logic gates organized in rows. When performing the blend operation each logic gates selects either a bit of the first operand A0 or a bit of the second operand A1. The selection for each logic gate depends upon bits of the third operand X. More specifically, each of the plurality of rows of logic gates selects the first operand A0 as output when an associated bit of the third operand X is at logic 1, and selects the second operand A1 as output when the associated bit of the third operand X is at logic 0. In addition to output generated by the plurality of rows of logic gates, a correction term is generated. For the blend operation, the correction term generated is the second operand A1. Partial product circuitry sums outputs of each row of logic gates and the correction term, to produce the result Z, so that the result Z has a value equal to X*A0+(1-X)*A1.
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