Error detection and correction for four-bit-per-chip memory system

摘要

Advantage is taken of the presence of identity submatrices in a parity check matrix to achieve correction of errors in a single symbol and detection of errors in a single symbol together with a single bit error in another symbol for use in computer memory systems. The code structure enhances utilization of chip real estate and specifically provides for the utilization of a (76,64) code which employs 19 chips per computer memory word as opposed to 20 chips per word.