| 摘要 |
The semiconductor memory device having a cell array of a folded bit line structure according to the present invention comprises main bit lines MB1 and MB2 and m sub-bit lines SB1i and SB2i (1</=i</=m), which detect amplifiers connected to both ends of the main bit lines, respectively, two sub-bit line block selection switching means for connecting the main bit line with respective sub-bit lines according to a block selection signal SBi, and a main bit line separation switching means connected between the two sub-bit line block selection switching means, for dividing the main bit line into two equal parts according to a main bit line separation signal. The number of cells connected to the bit lines is increased and the number of whole detect amplifiers is decreased, which may reduce the size of the chip so as to reduce the fabricating costs of the memory product./!
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