Method of decoupling the high order portion of the addend from the multiply result in an FMAC

摘要

A method and apparatus for decoupling the high order portion of the addend from the multiply result in an FMAC (floating-point multiply accumulate unit) such that the FMAC's datapath width is bounded to "2m+1"-bits, and the maximum width of required adders, shifters and leading bit anticipators is also bounded to "2m+1"-bits. The method and apparatus 1) reduce the necessary chip area for implementing an FMAC, and 2) reduce the length of routing paths through adders and shifters.