| 摘要 |
A circuit and method for transferring data between a first domain operating synchronously with respect to a first clock having a frequency C1 and a second domain operating synchronously with respect to a second clock having a frequency C2. The ratio of the clock frequencies is equal to the ratio of two integers. The data is to be transferred from a latch in the first domain to a latch in the second domain having setup and hold requirements to prevent race conditions. The circuit includes a plurality of data paths, each data path providing a different delay, the delays being quantized in units of 1/(2C1). The circuit also defines a first clock cycle in which the first clock has a predetermined relationship with respect to the second clock. The circuit selects one the plurality of data paths depending on a relationship between the first clock and the defined clock cycle. The path is selected such that the transferred data arrives at the latch in the second domain with the minimum delay consistent with the setup and hold requirements of the latch in the second domain. The circuit may also include a FIFO buffer. In this case, data stored in the FIFO is delivered to the second domain via one of a plurality of paths, each the path having a different delay, the delays being quantized in units of 1/(2C1).
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