发明名称 CIPHERING AND DECIPHERING DEVICE
摘要 PROBLEM TO BE SOLVED: To accelerate the processing speed by processing data at the high-order part of a register and decreasing the number of instructions when the register length is long. SOLUTION: For example, three 32-bit dataα0 ,α1 , andβare received; and their high-order 8-bit parts are denoted as a0 , a1 , and b0 and the low-order 8-bit parts are denoted as a3 , a2 , and b1 . An XOR process part 110 exclusively ORs those data, bit by bit, and stores the results in a register T1 . Here, outputs (a1 )1 and (a2 )1 of parts which vary in value are arranged in the high-order and low-order 8-bit parts of the register T1 . Therefore, two processes can be performed by one operation. Then an S box process part 110 operates S((a1 )1 , (a2 )1 , and 1). Consequently, the low-order 8 bits of the register T1 are arranged at the high-order 8 bits of a register T2 , T3 =T1 +T2 +2<24> is calculated, and the result is stored in a register T3 . At this time, digit overflows are all ignored. Similar calculates are repeated.
申请公布号 JPH10133575(A) 申请公布日期 1998.05.22
申请号 JP19960285030 申请日期 1996.10.28
申请人 NIPPON TELEGR & TELEPH CORP <NTT> 发明人 UEDA HIROKI;ABE MASAYUKI;FUJIOKA ATSUSHI
分类号 G09C1/00;(IPC1-7):G09C1/00 主分类号 G09C1/00
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