| 摘要 |
<p>PROBLEM TO BE SOLVED: To shorten arithmetic time, to prevent circuit scale from being expanded and to prevent the provision of butterfly operation on a hard-ware from being disturbed by unnecessitating a complex adder/subtracter when providing the butterfly operation for the 1st stage of time thinned fast Fourier transformation of a radix '2' on the hardware. SOLUTION: At an arithmetic data storage part 6, 2M pieces of combination expressed by M bits are allocated to 2M kinds of complex data of L bits and when the butterfly operation of the radix '2' is performed while inputting two pieces of 2M kinds of arbitrary complex data of L bits, the combination of two pieces of 2<2> M kinds of complex data existent as the arithmetic result is stored. In this case, any one of 2<2> M pieces of combination expressed by 2M bits inputted from a timing control part 5 is selected and outputted as the butterfly operation result on the 1st stage of butterfly operation of time thinned fast Fourier transformation of the radix '2'.</p> |
