| 摘要 |
PROBLEM TO BE SOLVED: To shorten a lockup time and to realize reception at an optimum tuning point with a high speed PLL circuit employing rough tuning and fine tuning. SOLUTION: The radio receiver is provided with a VCO 10 that includes a rough adjustment voltage controlled diode 100 and a fine adjustment voltage controlled diode 101, with a voltage synthesis circuit 13 that applies a rough adjustment control voltage VS outputted from a D/A converter 12 depending on frequency division data to the rough adjustment voltage controlled diode 100, applies an output voltage of a low pass filter in a PLL circuit to the fine adjustment voltage controlled diode 101 as a fine adjustment control voltage VT, and synthesizes the rough adjustment control voltage VS and the fine tuning control voltage VT in response to frequency change rates Δfs, Δft with respect to the control voltage applied to the rough adjustment voltage controlled diode 100 and the fine adjustment voltage controlled diode 101, and applies a synthesized voltage VTA to the antenna tuning circuit 2. |
