| 摘要 |
PROBLEM TO BE SOLVED: To provide a method which easily generates various combinations of test pattern in a simulation process. SOLUTION: A signal generating controller 1, which comprises an initializing processor 6, a signal generating processor 7, and a finalizing processor 8, refers to a parameter file 2 containing parameter detailed information and a control file 3 containing generating schedules, and communicates data or others with a VHDL simulator 5 through an interface section 4. The signal generating controller 1 creates single or plural signal generating regions, specifies single or plural signal generating regions sequentially according to a generating schedule read from the control file 3, and outputs the test pattern corresponding to the parameter which is set for each signal generating region. |
