发明名称 Method for fabricating a NPN transistor in a BICMOS technology
摘要 <p>An npn bipolar transistor, formed in an epitaxial layer within a window delimited in a thick oxide layer (102), includes (a) an opening formed at the centre of the window and extending into the epitaxial layer (101) to a depth of at least the same order as the thickness of the thick oxide layer, the opening walls being coated with a silicon oxide layer (110) and a silicon nitride layer (120); (b) a polysilicon spacer (121) formed on the side walls and part of the bottom wall of the opening; (c) a heavily n-doped polysilicon layer (123) formed in the opening and in contact with the epitaxial layer at the bottom of the opening within the space delimited by the spacer (121); (d) an n-doped region (125) at the bottom of the opening; and (e) a first p-doped base region (114) at the bottom of the opening, a second lightly p-doped region (115) on the sides of the opening and a third heavily p-doped region (112) formed near the top of the opening and in contact with an n-doped polysilicon layer (105), the three p-type regions being contiguous and forming the base of the transistor. Also claimed is a process for producing an npn transistor in an n-type epitaxial layer.</p>
申请公布号 EP0843351(A1) 申请公布日期 1998.05.20
申请号 EP19970410132 申请日期 1997.11.18
申请人 STMICROELECTRONICS S.A. STMICROELECTRONICS S.A. 发明人 GRIS, YVON
分类号 H01L29/73;H01L21/331;H01L21/8249;H01L27/06;H01L29/08;H01L29/10;H01L29/732;(IPC1-7):H01L21/331 主分类号 H01L29/73
代理机构 代理人
主权项
地址