ELECTRICALLY ERASABLE AND WRITABLE READ-ONLY MEMORY HAVING POLYSPACER FLOATING GATE

摘要

PROBLEM TO BE SOLVED: To obtain a topography advantageous for reducing the device by forming floating gates on the side walls of selection gates and control gates on the selection gates and floating gates through an insulation layer. SOLUTION: On a semiconductor substrate 1 field oxide regions 3 between which drain and source doped regions are formed with a first insulation gate oxide layer 5 formed on the substrate 1. On the gate oxide layer selection gates 7 are formed and second insulation layer 9 is formed on the side walls of the selection gates 7 and floating gates 11 are formed on the sides of the first insulation layer 9. Control gates 17 are formed on the selection gates 7, second insulation layer 9 and floating gates 11. Lightly doped drains are e.g. formed between the drain and channel and the selection, floating and control gates 7, 11, 17 are made of polysilicon.