| 摘要 |
PROBLEM TO BE SOLVED: To provide an NOR type mask ROM suited for a highly integrated structure wherein the cell current is improved and stabilized. SOLUTION: Metal lines ML1-ML6 are alternately used as bit lines and ground lines. When bank select lines MBS1, MBS2 turn on a select transistor S, a bit line voltage and ground voltage are alternately sent to diffusion layer DB3 sub-bit lines SB1-SB5. By a high voltage of either sub-bank select line OBS or EBS the select transistor S selectively turns on to do the row selection. The word line selection provides selection between a right or left memory cell of the diffusion layer DB2 or DB3, thus reading NOR type cells. Such a double cell current route is formed to hold the diffusion layer resistance const., irrespective of the memory cell position and suppress the resistance. The channel width of the transistor S can be made large because of the setting in the length direction of the diffusion layer, thereby improving the current driving power enough. |
