| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a motion compensated adder which accelerates motion compensation processing in a microprocessor that has sum of products operation. SOLUTION: A pixel value of a predictive image that is represented by an unsigned number is loaded to a register (84), and the most significant bit is reversed (85) and undergoes a format transformation to a signed number with -128 offset. When a hexadecimal constant 0x01000000 as a multiplicand, a signed error value as a multiplier and a pixel value of a predictive image after format transformation which is stored in the most significant byte of a register as an additional value are given to a sum of products operation instruction that has a clipping function (68), the sum of products operation instruction performs addition of the pixel value of a predictive image which is needed for motion compensation addition processing and the error value and clipping processing in one instruction.</p> |
