摘要 |
<p>PROBLEM TO BE SOLVED: To provide a system controller which interlocks frequency switching or supply stop of a CPU clock, controls an operational clock of internal another circuit and improves effect of saving the power by not only limiting reduction of the power consumption that accompanies frequency drop to a CPU but also extending it to internal circuits such as an IO controller, etc. SOLUTION: When a clock controlling part 16 receives a state detection signal (STP-GRT) of stop grant state under the setting of a power save mode flag by a clock signal, it outputs a clock stop control signal (SPXCK), disconnects the supply of a CPU clock to a CPU 11 and also disconnects an operational clock to an ISA bus controlling part 15, a DMA(direct memory access) controller 17, an infrared communication controller 18, a serial I/O controller 19, etc.</p> |