| 摘要 |
PROBLEM TO BE SOLVED: To attain reduction of cost, low power consumption and shortening of testing time due to reduction in size of circuit by arranging an FF circuit for scanning cell in the first and final stages of the shift register for scanning. SOLUTION: In a semiconductor integrated circuit having a shift register circuit for scanning, a shift register circuit 10 for n-bit scanning inputs an output data of a combining circuit 11 in the input side and serially fetches this input in synchronization of a clock pulse signal for the purpose of shifting. A combining circuit 12 in the output side inputs a serial output data of the shift register circuit 10 for scanning. The shift register circuit 10 for scanning replaces the D-type FF circuit in the first stage and the D-type FF circuit in the final stage among the D-type FF circuits of the n-bit shift register circuit with the FF circuit 90 for scan cell and uses an ordinary D-type FF circuit 20 as it is for the intermediate stage. |
