发明名称 PLL
摘要 PROBLEM TO BE SOLVED: To provide a PLL whose synchronization is set up with respect to an input signal, even when a dead band is in existence in a voltage controlled oscillator(VCO) control circuit. SOLUTION: A comparator 11 compares an output voltage of a filter 63 with a reference voltage to output the comparison result to a charge pump 12. A charge signal or a discharge signal, based on a phase difference between a phase of an input signal and that of an output clock signal, is given to the charge pump from a phase comparator 61, the charge pump 12 conducts charging/discharging of the filter 63 based on the signals. When an output of the comparator 11 indicates that the output voltage of the filter is lower than the reference voltage, the discharge signal is inactivated. In this case, the charge pump responds to only the charge signals. The filter generates a voltage in response to the charge amount. A VCO control circuit 64 generates a current in response to the input voltage. A VCO 65 controls the frequency of a clock signal in response to the input current.
申请公布号 JPH10126259(A) 申请公布日期 1998.05.15
申请号 JP19960276313 申请日期 1996.10.18
申请人 NEC CORP 发明人 HAYATA MASAAKI
分类号 H03L7/095;H03L7/089;H03L7/093;H03L7/099;H03L7/10 主分类号 H03L7/095
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