发明名称 VARIABLE DELAY CIRCUIT AND BIT PHASE SYNCHRONIZATION CIRCUIT
摘要 PROBLEM TO BE SOLVED: To prevent duty ratio deterioration and effectively utilize the output signal of an odd-numbered inverter for some purpose in addition to a duty guarantee by connecting even-ordered and odd-numbered inverters which has constant delay times to different selectors, and independently selecting their output signals. SOLUTION: A system clock ck from an input terminal IN is inputted to delay circuit inverters 111 to 112n , which are cascaded. Those delay circuit inverters 111 to 112n have constant propagation delay times and the even- numbered and odd-numbered inverters are connected to input terminals s1 to sn of the selectors 12 and 13. Further, select signals s11 and s12 are connected to the selectors 12 and 13 from outside, and output signals S10a and S10b are outputted. Through this variable delay circuit constitution, the output signals of the even-numbered inverters and the output signals of the odd-numbered inverters can be selected independently.
申请公布号 JPH10126399(A) 申请公布日期 1998.05.15
申请号 JP19960271165 申请日期 1996.10.14
申请人 OKI ELECTRIC IND CO LTD 发明人 YOSHIDA SATOSHI;YAMAOKA SHINSUKE;MATSUMOTO SHUICHI
分类号 H03K5/13;H04L1/22;H04L7/00;H04L7/02 主分类号 H03K5/13
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