发明名称 |
Integrierte Masterslice-Schaltung mit reduzierten Chipabmessungen und vermindertem Speisespannungsrauschen |
摘要 |
In a master slice integrated circuit, a number of connection pads are located in a peripheral edge region of a chip in such a manner that each one power supply pad is interposed between each pair of signal input/output pads and a number of unitary pad arrays each of which consists of a signal pad, a power supply pad and another signal pad located in the named order are repeatedly arranged along a peripheral edge of the chip. Thus, the pad pitch can be reduced to two thirds of the width of an I/O cell, without changing the I/O cell size. In addition, since the power supply pad is located adjacent each of the I/O cells, it is effective to suppress or minimize the power supply voltage noise caused by the simultaneous driving. <IMAGE> |
申请公布号 |
DE69314686(T2) |
申请公布日期 |
1998.05.14 |
申请号 |
DE1993614686T |
申请日期 |
1993.04.01 |
申请人 |
NEC CORP., TOKIO/TOKYO, JP |
发明人 |
IRUKA, MASAO, C/O NEC CORPORATION, TOKYO, JP |
分类号 |
H01L21/82;H01L27/02;H01L27/118 |
主分类号 |
H01L21/82 |
代理机构 |
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代理人 |
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