| 摘要 |
An input signal reading circuit comprises an up-down counter receiving an input signal and a sampling clock to count up the sampling clock when the input signal is at a high level and to count down the sampling clock when the input signal is at a low level. The up-down counter outputs an underflow signal when a count value of the up-down counter becomes zero. A comparator compares the count value of the up-down counter with a reference value held in a register, to generate a coincidence signal when the count value of the up-down counter becomes coincident with the reference value. A RS flipflop is set by the coincidence signal to bring the read-out signal into a high level, and is reset by the underflow signal to bring the read-out signal into a low level. <IMAGE> |
