发明名称 |
Method and apparatus for avoiding writeback conflicts between execution units sharing a common writeback path |
摘要 |
Pipeline lengthening in functional units likely to be involved in a writeback conflict is implemented to avoid conflicts. Logic circuitry is provided for comparing the depths of two concurrently executing execution unit pipelines to determine if a conflict will develop. When it appears that two execution units will attempt to write back at the same time, the execution unit having a shorter pipeline will be instructed to add a stage to its pipeline, storing its result in a delaying buffer for one clock cycle. After the conflict has been resolved, the instruction to lengthen the pipeline of a given functional unit will be rescinded. Multistage execution units are designed to signal a reservation station to delay the dispatch of various instructions to avoid conflicts between execution units. |
申请公布号 |
GB2287108(B) |
申请公布日期 |
1998.05.13 |
申请号 |
GB19940016585 |
申请日期 |
1994.08.17 |
申请人 |
* INTEL CORPORATION |
发明人 |
ROBERT P * COLWELL;MICHAEL ALAN * FETTERMAN;ANDREW F * GLEW;GLENN J * HINTON;ROBERT W * MARTELL;DAVID B * PAPWORTH |
分类号 |
G06F9/38;(IPC1-7):G06F9/28 |
主分类号 |
G06F9/38 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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