High planarity, low CTE base and method of making the same

摘要

The present invention relates to a system and method for performing reliability screening on semi-conductor wafers and particularly to a highly planar burn in apparatus and method for uses including wafer level burn-in (WLBI), diced die burn-in (DDBI), and packaged die burn-in (PDBI). The burn-in system includes a burn-in substrate with a planar base. a temporary Z-axis connecting member, and a Z-axis wafer level contact sheet electrically coupled to one another for screening wafers, diced die, and packaged electronic components, their assembly and use.