| 摘要 |
1529638 Data processing TELEFONAKTIEBOLAGET LM ERICSSON 10 May 1976 [14 May 1975] 19189/76 Heading G4A In a data processing system comprising a number of functional units FU to execute instructions and a central instruction store all interconnected by common instruction and data buses, the instructions, accessed from the store in successive read phase times, are of two types, the first having an address part specifying a functional unit and an operational part specifying an operation to be performed by that unit in the read phase following that in which the instruction was accessed, and the second having two address parts specifying functional units to transmit and receive data respectively via the common data bus during the read phase following that in which the instruction was accessed and an operational part specifying an operation to be performed by the data receiving functional unit. The address part of a first type instruction received over bus AB1 activates decoder ADEC1 in the specified unit while the operational part received over bus OB is decoded, ODEC, to activate the appropriate one of the lines 01. Near the end of the read phase in which the instruction was accessed, the read phases being delineated by pulses #p, a pulse #e occurs and the appropriate gate G1 conducts to activate the corresponding element E 1 to cause the operation to be performed by logic L in the following read phase. The first address part of a second type instruction activates decoder ADEC1 in the specified (transmitting) unit but the gates G1 remain blocked since no signals 01 exist. However a signal 02 does exist so that, via OR gate 62, AND gate G3 becomes conductive on pulse #e, the gates G5 remaining blocked since decoder ADEC2 is inactive. At the following pulse #p, i.e. during the subsequent read phase, the resulting bit in shift register SRI is shifted to enable gate RG and gate the contents of register DR on to the data bus DB. The second address part of the instruction activates decoder ADEC 2 in the specified (receiving) unit, and via shift register SR2, enables gate WG to connect the register DR to the data bus to receive data during the same subsequent read phase. In the receiving unit the operational part of the instruction is decoded to activate the appropriate one of the lines 02 which, because of the output from ADEC2 and AND G4, activates the appropriate one of the elements E2 via a gate G5 to cause the specified operation to be performed with the received data. In a modification the operational part of an instruction includes two parts with respective decoders corresponding to signals 01 and 02 above, the second part corresponding with the second address part of a second type instruction and being sent over the bus in the read phase following the phase in which the instruction was accessed so that the shift register SR2 to delay the actuation of the receive gate WG is omitted. |
