| 摘要 |
The present invention is for an implementation of a multi-stage digital decimation filter and a method of decimating a multi-bit input signal, where n/2 additions are performed, where n=the number of bits in each filter coefficient. A compensation stage is also provided. Scaling and multiplication of data with coefficients is performed using a common architecture to the Decim. 2 and Decim. 3 stages. Coefficient values, having an associated scaling factor, are stored in memory. The coefficients are stored in coded form, and are then decoded prior to multiplication by the data values.
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