发明名称 |
DRAM with reduced leakage current |
摘要 |
A DRAM with reduced leakage current includes at least two line driving means for transmitting high potential to a line selected by an address signal externally input; a main power line for transmitting a power source voltage externally supplied; secondary power lines for transmitting the power source voltage to the respective line driving means; switching means respectively connected between the main power line and secondary power lines; block selection means for outputting a signal where two block selection addresses are logically combined, to each of the line driving means, in order to select and operate one of the line driving means; and switching control means for outputting a signal which controls each of the switching means through the logical combination of the output signal of the block selection means and a refresh operation mode signal.
|
申请公布号 |
US5751653(A) |
申请公布日期 |
1998.05.12 |
申请号 |
US19970867455 |
申请日期 |
1997.06.02 |
申请人 |
HYUNDAI ELECTRONICS INDUSTRIES CO., LTD. |
发明人 |
CHUNG, IN SOOL;LEE, JAE JIN |
分类号 |
G11C11/407;G11C11/406;G11C11/408;(IPC1-7):G11C13/00 |
主分类号 |
G11C11/407 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|