Method and apparatus for simultaneously executing instructions in a pipelined microprocessor

摘要

An instruction combination unit for a microprocessor compares multiple fetched instructions to determine whether they can be combined for simultaneous execution. The instruction combination unit compares destination registers of preceding instructions against source registers of subsequent instructions. If a subsequent instruction is to operate on a result of a preceding instruction before the result of the preceding instruction is available to the subsequent instruction, a data access conflict arises. The instructions are compared, and combined, if possible. Otherwise, execution of the subsequent instruction is stalled until the result from the preceding instruction is available to the subsequent instruction.