| 发明名称 |
CLOCK SYNCHRONIZATION CIRCUIT BETWEEN CENTRAL PROCESSORS |
| 摘要 |
<p>PURPOSE:To enable to access the same memory, by waiting the readout cycle of one processor until the readout cycle of other processor is finished and by reading out it after the end of waiting.</p> |
| 申请公布号 |
JPS5436152(A) |
申请公布日期 |
1979.03.16 |
| 申请号 |
JP19770102954 |
申请日期 |
1977.08.26 |
| 申请人 |
NIPPON ELECTRIC CO |
发明人 |
FUKASE TAKAYUKI |
| 分类号 |
G06F1/04;G06F1/12;G06F12/00;G06F13/00;G06F15/16;G06F15/177 |
主分类号 |
G06F1/04 |
| 代理机构 |
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代理人 |
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| 主权项 |
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| 地址 |
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